This invention relates to a very large scale integrated circuit (VLSI) which comprises a number of function cells which are connected to one another and to the environment by means of information connections.
Chapter 7 (by C. L. Seitz) of Mead & Conway's book, Introduction to VLSI systems, Addison-Wesley, Philippine Copyright 1980, describes the problems relating to the mutual synchronization of various elements of the circuit. These problems increase as the technology develops towards very large scale integration (VLSI), because the switching times of active elements (gates, transistors) decrease rapidly as their dimensions decrease, while the transport times of information signals via connections between these active elements decrease less rapidly. Furthermore, the number of active elements on one chip continually increases, so that the physical dimensions of the circuits are not reduced systematically. Consequently comparatively speaking, the maximum signal transport time across the circuit remains the same over the years. The duration of signal transports between neighboring circuit elements is usually not objectionable, but the requirement that an arbitrary transport within the circuit must be performed sufficiently quickly either imposes an upper limit on the feasible operating speed, for example as defined by a clock frequency, or imposes a set of restrictive and sometimes contradictory restrictions on the relative positions of various active elements, because the elements which communicate with one another may not be situated too far apare in a synchronous system.
The latter implies an increasing complexity of the design methodology of very large scale integrated circuits. Another problem, caused by the increasing number of switching elements (gate equivalents) on a chip, is the complexity of the necessary test procedures. For circuits which are not excessively large an attractive method has been proposed by Eichelberger (U.S. Pat. No. 3,761,695), but the complexity of this test method also increases rapidly, because each bistable element of the circuit must receive an information bit. In the case of a large number of such bistable elements, the length of the test patterns (bit series) and notably the length of the series of test patterns becomes too large to allow for complete testing within a limited period of time. It is to be noted that such a test may be performed on the physical circuit itself as well as on a simulated circuit which is stored in a computer memory in the form of interaction structures. Finally, the design of such a very large scale integrated circuit becomes increasingly more complex, as will be described hereinafter.